1. Field of the Invention
This invention relates to high voltage integrated circuit semiconductor devices and more particularly to level shift high voltage semiconductor devices.
2. Description of Prior Art
In high voltage integrated circuits (HVIC) it is desirable to utilize high voltage push-pull output circuits. Further, when the device sourcing current is an N-channel or P-channel MOS transistor in a HVIC, the gate of the device must be driven on and off relative to this high voltage supply. For example, a P-channel device can be turned on by pulling its gate 20 volts below its source. If a 200 volt supply is used, the gate would be pulled down to 180v Similarly, it can be turned off by taking the gate potential to the 200 volt supply potential. The control signals normally available for turning devices on and off are referenced to ground and vary between 0 to 20 volts (or in some cases between 0 and 5 volts). It will quickly be appreciated that in order to turn a device "on" and "off", such as the P-channel device noted above, it will be necessary to produce high voltages from the above-noted normally available relatively low control voltages. The circuit which performs this function is known as a high voltage level shifter. This may be done in several ways, either through a high voltage cross-coupled pair or a high voltage resistor-load inverter circuit. A typical prior art high voltage resistor-load inverter circuit is illustrated in FIG. 1. Referring to FIG. 1, resistor-load inverter circuit 1 includes low voltage logic input circuit 2, depicted in FIG. 1 in block form, having a range of potential from 0 to 20 volts in this circuit, but as noted above, a control signal of from 0 to 5 volts may be used in some circumstances. Logic circuit 2 is utilized to turn "on" and "off" high voltage N-channel transistor 3. Transistor 3 includes gate 4, which receives control signals from logic input circuit 2, source 5 which is connected to body 6, both of which are commonly connected to ground and drain 7 which is connected to the lower side of resistor 8. The upper side of resistor 8 is connected to a positive high voltage line, which would typically be between 100 volts and 500 volts, obtained from supply from pad 9. To complete circuit 1, high voltage P-channel transistor 10 is included having its gate 11 connected to a tap (unnumbered) of resistor 8, its source 12 and body 13, which are commonly connected, which are tied to the positive high voltage supply. Transistor 10 also includes drain 14 which is connected to output pad 15. As mentioned above, it is desired to turn device 10 "on" and "off" which requires bringing gate 11 to approximately 20 volts below the potential on the +HV line to turn device 10 "on", and returning gate 11 to the +HV volt supply potential to turn device 10 "off". Shifting gate 11 of device 10 between the above-mentioned voltages is accomplished by appropriate control signals to gate 4 of device 3 to turn device 3 "on" and "off" changing the potential at the tap of resistor 8, causing the potential on gate 11 to shift between the +HV supply potential when device 3 is "off" and to drop to approximately 20 volts below the +HV supply potential when device 3 is "on". Although the P-channel device in circuit 1 is shown as an MOS transistor, such a circuit may also be implemented using a PNP bipolar transistor instead of transistor 10, however the circuitry may be different.
To implement high voltage level shift circuit 1 monolithically, metal interconnects must cross high-voltage PN junctions. When a metal interconnect crosses a high voltage PN junction, it concentrates electric fields which can lead to breakdown at the junction. Techniques are available to field plate the high voltage junction to alleviate the problems caused by a high voltage interconnect crossing above the junction, but the field plate technique is increasingly difficult to implement at higher voltages and may be incompatible with certain wafer fabrication processes.
FIG. 2 illustrates the cross-section of a portion of a lightly doped drain of N-channel device 3 having source 5 and body 6 shorted by metallization 22 as described above with respect to circuit 1. Referring to FIG. 2, the reverse biased equipotentials are illustrated for the "off" state condition. More particularly, it will be noted that since drain 7 is connected via metallization 18 to high voltage (through resistor 8, not shown), equipotential lines varying from 0 volts to 180 volts are distributed across substrate 19 and pose a crowding problem in region 20 where the equipotential lines converge near the lightly doped end of drain extension 7a. With the converging of these lines at junction 21 (the PN junction between substrate 19 and drain extension 7a) the likelihood of breakdown in this region is dramatically increased.
Implementing circuit 1 utilizing a self-isolated high voltage integrated circuit process will result in at least four high-voltage interconnect points which will occur on the topography required to monolithically implement circuit 1. The term "self-isolated" is used because, with respect to FIG. 2 for example, drain 7 forms back-to-back diodes with the drain of any adjacent N-channel device. FIGS. 3 and 4 (which will be described after FIG. 3) show a typical implementation of circuit 1. Referring to FIG. 3, these interconnect points are illustrated on the schematic by including dashed lines representing N-well regions 28 and 30, and more specifically include point 25, which is the high voltage crossing of metallization 18 to drain 7 of N-channel transistor 3; point 26 where metallization 18 crosses the P substrate (which is below metallization 18) leading to the junction with resistor 8; point 27 where metallization 44 crosses into N-well 28 to the tap point (unnumbered) of resistor 8; and point 29 where metallization 44 crosses the PN junction to reach N-well region 30 where metallization 44 connects to gate 11 of P-channel transistor 10. The P-channel device may be self-isolated in an N-well region or be a DMOS device with N+isolation region, in which case there will be a high voltage crossing of the N+isolation region. In addition, if the high voltage supply bonding pad 9 is not located inside N-well region 28, high voltage crossing point 31 will be encountered, and similarly, if the high voltage crossing to source 12/body 13 connection on P-channel device 10 is outside of region 30, high voltage crossing point 32 will also occur.
Referring to FIG. 4, there is illustrated in a top plan view the typical topography used to layout prior art circuit 1. Common ground bus 34 runs along the lower edge of cell 35 and is connected to body 6 and source 5 of N-channel device 3 at connection points 36 and 37, respectively, and is also connected to logic block 2. Via metallization 38, logic block 2 is connected to gate 4 of N-channel device 3. Bus 39 connects drain 7 to a connection point 40 of resistor 8 in circuit 1. It will be appreciated that with these connections, crossing points 25 and 26 (indicated in FIG. 4 by dashed lines to denote the regionlike nature of the crossing points) are encountered. As is well known in the prior art, resistor 8 is fabricated through the use of N-well regions 28a and 28b, which are located within guard ring 41 of highly P-doped material. Regions 28a and 28b may be formed, for example, by a diffusion process and would be N-doped regions in P-type substrate 19. Contact points 42 and 43 connect metallization 44 to regions 28a and 28b and form the tap connection to resistor 8. Bus 44 continues above substrate 19 and crosses above the junction between substrate 19 and N region 30, and connects to gate 11 of P channel device 10. This routing of metallization 44 results in crossing point 27 and crossing point 29. Positive high voltage bus 45 provides connection to region 28b of resistor 8 and results in crossing point 31 and 31'. Crossing point 32 from high voltage pad 9 into N-well region 30 may also be noted by reference to FIG. 4.
Also illustrated in FIG. 4 is body region 13 of P-channel device 10, source region 12, both of which are connected via contact points 46 and 47, respectively to high voltage bus 45. From the foregoing, it will be appreciated that with the prior art circuit numerous problem crossing points are encountered where a high voltage crosses a PN junction in the typical prior art layout as illustrated in FIG. 4.